The present disclosure relates to a liquid crystal panel driving apparatus and, more particularly, to a liquid crystal panel driving apparatus including a plurality of timing controllers.
A conventional liquid crystal driving apparatus, which drives a high resolution liquid crystal panel using a plurality of timing controllers and allows a large amount of display data can be transmitted at lowered the transmission rates, is known. FIG. 4 is a block diagram of a conventional liquid crystal panel and a liquid crystal driving apparatus. A graphic processor 300C provides a timing controller 100C with a display data signal DD1C, and provides a timing controller 200C with a display data signal DD2C. The timing controller 100C provides each of source drivers 410C-1 to 410C-N (where N is a positive integer) with a source driver control signal SD1C and an image data signal PD1C based on the display data signal DD1C. In addition, the timing controller 100C provides each of gate drivers 510C-1 to 510C-M (where M is a positive integer) with a gate driver control signal GD1C based on the display data signal DD1C. The source drivers 410C-1 to 410C-N and the gate drivers 510C-1 to 510C-M drive a liquid crystal panel 600C in accordance with the source driver control signal SD1C, the image data signal PD1C, and the gate driver control signal GD1C received from the timing controller 100C. The timing controller 200C, the source drivers 420C-1 to 420C-N, and the gate drivers 520C-1 to 520C-M operate in a substantially similar manner using the source driver control signal SD2C, the image data signal PD2C, and the gate driven control signal GD2C.
In the configuration as shown in FIG. 4, the timing controller 100C and the timing controller 200C usually operate independently from each other. In some devices, the timing controller 100C has an alarm function in order to protect the liquid crystal panel 600C when the display data signal DD1C is abnormal, and, similarly, the timing controller 200C has an abnormality display function in order to protect the liquid crystal panel 600C when the display data signal DD2C is abnormal. In such a configuration, the normal and the abnormal signals are displayed together at the same time, for example, in the case where only the display data signal DD1C is abnormal. Furthermore, when the control timing of the gate drivers 510C-1 to 510C-M according to the timing controller 100C and the control timing of the gate drivers 520C-1 to 520C-M according to the timing controller 200C are different from each other, there is a possibility that the gate drivers 510C-1 to 510C-M, the gate drivers 520C-1 to 520C-M, and the liquid crystal panel 600C may be damaged.
Japanese Laid-Open Patent Application Publication No. 2006-243565, which is incorporated by reference, discloses a method of driving a display panel using a plurality of timing controllers. In particular, when one of the timing controllers detects an abnormality in the display control, the timing controller informs the other timing controller of the detection result, and then damage to the display panel can be prevented by the normal display control by transmission of normal image data and a normal clock signal to one of the timing controllers by the other controller.
However, Japanese Laid-Open Patent Application Publication No. 2006-243565 does not provide a description of the case where each of a plurality of the timing controllers simultaneously receives abnormal display data, and no specific circuit configuration to cope with this situation is disclosed. Further, there is no description of a countermeasure to the case where abnormal display data different between the timing controllers are inputted. For example, there is no description of a case in which a display data signal missing a clock signal is provided to one of the timing controllers, and a display data signal missing a synchronization signal is provided to the other timing controller. Consequently, the display panel driving method disclosed in Japanese Laid-Open Patent Application Publication No. 2006-243565 has a problem that the normal signal and the abnormal signal are displayed together at the same time in the case where each of the plurality of timing controllers simultaneously receives the abnormal display data. Additionally, there is no description of synchronization between image display timing of the plurality of the timing controllers, and there is a problem that the liquid crystal panel may be damaged due to unsynchronized gate-driver control timing between the timing controllers.